Frequency synthesizers are used in virtually all wireless devices to create the fundamental frequency at which the wireless device operates. Wireless communications often need to change the frequency of operation. The amount of time required to change the frequency of the wireless device is normally time during which the wireless device cannot function normally, that is it cannot transmit or receive data when changing frequencies. Wireless applications are very cost sensitive, hence a method to achieve fast switching of frequencies is very important. Reliability of wireless devices is also very important, and analog methods tend to be larger, cost more and are often less reliable than their digital counterparts. Most modern integrated frequency synthesizers use a device known as a phase frequency detector (PFD) which measures the difference in phase and frequency between the reference (REF) and the voltage controlled oscillator (VCO). The classic PFD suffers from a problem known as cycle slipping which results in longer times to change frequency. The REF and VCO inputs are acted upon by the PFD which creates output UP and DOWN switching signals which in turn drive current onto a loop filter that controls the voltage controlled oscillator. When the REF and VCO signals are in phase, both up and down pulses are short and equal. When the synthesizer changes frequency, initially the VCO signal frequency is no longer equal to the REF signal frequency. If the VCO frequency is slightly different than the REF, then the phase error will build up and the up/down pulses will have different durations, proportional with the phase error. As the error increases, the charge pump will be ON longer, thus the charge pumped into the loop filter will increase proportionally. However, when the phase error exceeds 360 degrees, it wraps back to zero and the overall result is that the charge pump is turned ON for very short periods of time, thus the correction charge pushed into the loop filter drops back toward zero, despite the fact that significant errors exist in frequency. This causes the VCO divided signal to slip a cycle relative to the REF, and the rate of tuning of the VCO in the direction of the desired new frequency will decrease or possibly even reverse temporarily. The net result is that the time for the VCO to change from the start frequency to the final frequency increases, and the overall time to lock to the new frequency also increases. One approach detects that a cycle slip is about to occur and turns on an extra charge pump current cell. This outputs a constant current to the loop filter, or removes a constant current from the loop filter (depending on whether the VCO tuning voltage needs to increase or decrease to acquire the new frequency). The effect is that the linear range of the PFD is increased. Stability is maintained because the current is constant and is not a pulsed current. If the phase error increases again to a point where another cycle slip is likely, it turns on another charge pump cell. This continues until it detects that the VCO frequency has gone past the desired frequency. It then begins to turn off the extra charge pump cells one by one until they have all been turned off and the frequency is settled. A drawback of this approach is that it requires extra analog circuitry which adds cost, complexity, and parasitic capacitance to the pump, thus limiting its upper frequency of operation. In most applications, it is enough to eliminate cycle slips altogether, giving much faster lock times. Other approaches apply similar techniques which may be quite complex. Some require more complex and sensitive timing of the VCO, others a complex mix of muxes and counters.